Intel Agilex Variable Precision Dsp Blocks Design Considerations; Fixed-Point Arithmetic; Configurations For Input, Pipeline, And Output Registers - Intel Agilex User Manual

UG-20213 | 2019.04.02
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4. Intel Agilex Variable Precision DSP Blocks Design
Considerations
You should consider the following elements in your design:
Table 23. Design Considerations
DSP Functions

Fixed-point arithmetic

Floating-point arithmetic
4.1. Fixed-Point Arithmetic

4.1.1. Configurations for Input, Pipeline, and Output Registers

The configurations for the input, pipeline, and output registers are restricted due to
the timing model in Intel Agilex devices. Therefore these registers only support certain
configurations.
Restrictions for Input Registers
The following are the clock enable restrictions for input registers:
• When using 9 x 9 sum of 4 operational mode, the following input signal pairs must
use the same clock enable settings:
—
ax
—
ay
—
cx
—
cy
•
If the input registers for
enabled, these registers must use the same clock enable settings.
•
Disable the input registers for
signals if these signals are driven by a constant value.
Restrictions for Pipeline Registers
The following are the clock enable restrictions for pipeline registers:
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and
bx
and
by
and
dx
and
dy
,
SUB NEGATE
Design Elements
• Operational modes
• Input, pipeline, and output registers
• Internal coefficient and pre-adder
• Accumulator
• Chainout adder
• Input cascade
• Input, pipeline, and output registers
• Operational modes
• Chainout adder
, , and
ACCUMULATE
, ,
SUB NEGATE ACCUMULATE
signals are
LOADCONST
, and
LOADCONST
ISO
9001:2015
Registered