Features; Table 13. Uart Point-To-Point Topology Platform Routing Guidelines - Intel Quark SE Series Platform Manual

Table 13. UART Point-to-Point Topology Platform Routing Guidelines

TXD, RXD, RTS, CTS
Transmission Line Segment
Stackup Layer (Microstrip/
Stripline/Dual Stripline)
Characteristic Impedance
Trace Width (w)
Min Trace Spacing (S1):
Between UART signals
Min Trace Spacing (S2):
Between UART signals and
other signals
Trace Segment Length
Total Trace Length
Reference
Number of via allowed
6.2

Features

Both UART instances are configured identically. The following is a list of the UART
controller features:
 Operation compliant with the 16550 Standard




 Baud rate configurability between 300 baud and 2M baud


 Auto Flow Control mode as specified in the 16750 Standard

Hardware Flow Control
 Software Flow Control (when Hardware Flow Control is disabled)
 Hardware Handshake Interface to support DMA capability
 Interrupt Control

FIFO support with 16B TX and RX FIFOs
 Support of RS485


Intel® Quark™ SE Microcontroller C1000
Platform Design Guide
32
<10000 mils
VSS
3
Start bit
5 to 8 bits of data
Optional Parity bit (Odd or Even)
1, 1.5, or 2 Stop bits
Maximum baud rate is limited by system clock frequency divided by 16
Supported baud rates: 300, 1200, 2400, 4800, 9600, 14400, 19200, 38400,
57600, 76800, 115200; multiples of 38.4 Kbps and multiples of 115.2 Kbps
up to 2M baud
Differential driver/receiver is external to the SoC
Driver enable (DE) and Receiver enable (RE) outputs are driven from the
SoC to control the differential driver/receiver
UART
SoC Breakout
TL0
MS/SL
50Ω +/- 10%
3.5 mils minimum
4 mils
5 mils
<500 mil
Document Number: 334715-004EN
UART
Main Routing
TL1
MS/SL
50Ω +/- 10%
Meet impedance
2W
2W
TL0+TL1 < 10000 mil
June 2017