Features; Table 9. Uart Point-To-Point Topology Platform Routing Guidelines; Table 10. Uart Point-To-Point Topology Platform Routing Guidelines - Intel Quark D2000 Design Manual

Table 9. UART Point-to-Point Topology Platform Routing Guidelines
TXD, RXD, RTS, CTS
Transmission Line
Segment
Stackup Layer
(Microstrip/
Stripline/Dual Stripline)
Characteristic Impedance
Trace Width (w)
Min Trace Spacing (S1):
Between UART signals
Min Trace Spacing (S2):
Between UART signals
and other signals
Trace Segment Length

Table 10. UART Point-to-Point Topology Platform Routing Guidelines

Total Trace length and Length Matching Rules
Total trace length
No length matching required
Number of vias allowed
Via stub length
Reference Plane
• If nominal trace width is not possible in breakout area, use 4 mil as min trace width.
Choose a stack up so 50ohms will be min 4mils
Routing can also be extended to10-12" in which case a series Rs of 22 Ω close to the
driver will be necessary to avoid ring back TX - SOC driver, RX - UART driver Max speed
= 2MBaud.
6.2

Features

Both UART instances are configured identically. The following is a list of the UART
controller features:
 Operation compliant with the 16550 Standard
 Start bit

5 to 9 bits of data
 Optional Parity bit (Odd or Even)

1, 1.5 or 2 Stop bits
Intel® Quark™ Microcontroller D2000
Platform Design Guide
28
BRK OUT
L1
MS/SL
50Ω SE10%
Meet
impedance
5 mil
5 mil
0.5" max See Table 11
(brd+pkg)
UART
Main BRANCH
L2 L4
MS/SL MS/SL
50Ω SE10% 50Ω SE10%
Meet Meet
impedance impedance
2*w 5 mil
3*w 10 mil
1" max
Min
Continuous Ground Reference
Document Number: 333580-002EN
UART
BRK IN
L3
MS/SL
50Ω SE10%
Meet
impedance
5 mil
5 mil
0.5" max
Max
1-5"
November 2016