Intel Agilex Reset Release Ip - Intel Agilex Configuration User Manual

2. Intel Agilex Configuration Details
UG-20205 | 2019.04.03
User Mode
• The SDM drives the
impedance state. The device enters user mode. The entire device does not enter user mode at the same instant.
• The
nCONFIG
•
You may re-configure the device by driving
Device Clean
• In the Device Clean state the design stops functioning.
• Device cleaning zeros out all configuration data.
•
The Intel Agilex device drives
• The SDM drives the
JTAG Configuration
Note: You can perform JTAG configuration anytime from any state except the power-on and SDM startup state. The Intel Agilex
device cancels the previous configuration and accepts the reconfiguration data from the JTAG interface. The
must be held in a stable or low state during JTAG configuration. A falling edge on the
configuration.
Note:
The SDM only samples the
specified at power-on.

2.3. Intel Agilex Reset Release IP

Intel strongly recommends that you use Intel Agilex Reset Release IP in your design to provide a known initialized state for
your logic to begin operation.
The Reset Release IP is available in the Intel Quartus Prime Software, version 19.1 and later . This IP consists of a single
output signal,
nINIT_DONE
both FPGA First and HPS First configuration modes. Because gating clocks may interfere with logic timing, Intel recommends
that you use the
Note: This component is not yet available for Intel Agilex devices.
Send Feedback
pin high after initializing internal registers and releases GPIO pins from the high
INIT_DONE
pin should remain high in user mode.
and
CONF_DONE
pin low when device cleaning completes.
nSTATUS
pins at power-on and initiates bitstream configuration using the configuration scheme
MSEL
. The signal is the core version of the
nINIT_DONE
signal to hold your design in reset.
nINIT_DONE
pin from low to high.
nCONFIG
low.
INIT_DONE
nCONFIG
signal cancels the JTAG
nCONFIG
pin and has the same function in
INIT_DONE
Intel ® Agilex ™ Configuration User Guide
signal
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