Reference Clock Source Selection; Cpu Reset Push Button; Logic Reset Push Button; General User Input/Output - Intel Arria 10 User Manual

5. Board Components
683227 | 2023.07.12

5.6.3. Reference Clock Source Selection

Table 26.
J17, J16
J30

5.6.4. CPU Reset Push Button

Table 27.
S1
S2

5.6.5. Logic Reset Push Button

5.7. General User Input/Output

Table 28.
0000
0001
0010
0011
0100
0101
0110
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The HPS jumpers define the bootstrap options for the HPS—boot source, mode, HPS
clocks settings, power-on-reset (POR) mode and peripherals selection.
HPS Jumpers
Board Reference
OSC2_CLK_SEL [1:0]
HPS voltage selection
CPU Reset Push Buttons
Push Button
The input is driven by
HPS_NRST
.
HPS_COLD_RESET
The logic reset push button (S10) is an input to the MAX V CPLD 5M2210 System
Controller. This push button is the default reset for the CPLD logic and FPGA.
All user-defined push buttons, DIP switches and LEDs are connected to the MAX V
System Controller. The IO_MUX CPLD maps user-defined signals to FPGA I/Os as
defined in the GHRD. The following section describes the mapping table.
I/O MAX V Application Modes
User DIP Switch [3:0]
Schematic Signal Name
HPS_WARM_RESET
HPS_COLD_RESET
. The
HPS_WARM_RESET
Default FPGA mode
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
®
Intel
Description
Selects the source of OSC2 clock:
00—Select 25 MHz clock source
01—Select external source via SMA
connector
10—Select 33 MHz on-board oscillator
Short—HPS core voltage is 0.95V
Open—HPS core voltage is 0.9V
Description
push button.
push button.
input is driven by
HPS_NPOR
Description
continued...
®
Arria 10 SoC Development Kit User Guide
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