Standard Input-Only Port Operation - Intel 8XC196MC User Manual

Mnemonic
P0_PIN 1FA8H (MC, MD)
1FDAH (MH)
P1_PIN (MC, MD) 1FA9H (MC, MD)
6.2.1

Standard Input-only Port Operation

Figure 6-1 is a schematic of an input-only port pin. Transistors Q1 and Q2 serve as electrostatic
discharge (ESD) protection devices; they are referenced to V
an additional ESD protection device; it is referenced to V
current flow through Q3 to acceptable levels. At this point, the input signal is sent to the analog
multiplexer and to the digital level-translation buffer. The level-translation buffer converts the in-
put signals to work with the V
is Schmitt-triggered for improved noise immunity. The signals are latched in the P0_PIN or
P1_PIN register and are output onto the internal bus when P0_PIN or P1_PIN is read.
Internal Bus
Buffer
Read Port
Table 6-3. Input-only Port Registers
Address
Each bit of P0_PIN reflects the current state of the corresponding
port 0 pin.
Each bit of P1_PIN reflects the current state of the corresponding
port 1 pin.
and V digital voltage levels used by the CPU core. This buffer
CC SS
Vcc
PORT 0
Level
Data Register
Translation
Buffer
P0_PIN
Q D
LE
PH1 Clock
Vss
Figure 6-1. Standard Input-only Port Structure
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Description
and ANGND. Transistor Q3 is
REF
(digital ground). Resistor R1 limits
SS
V
REF
To Analog MUX
150 to 200 Ohms
R1
Q3
Vss Vss ANGND
I/O PORTS
V
REF
Q1
Input Pin
Q2
ANGND
A0236-01
6-3