Figure 287. Transfer Sequence Flow For Slave Receiver With Nostretch = 1; Figure 288. Transfer Bus Diagrams For I2C Slave Receiver - ST STM32WL55JC Reference Manual

RM0453
Symbol
f SCL clock frequency
SCL
t Hold time (repeated) START condition
HD:STA
Set-up time for a repeated START
t
SU:STA
condition
t Set-up time for STOP condition
SU:STO
Bus free time between a STOP and
t
BUF
START condition
t Low period of the SCL clock
LOW
t Period of the SCL clock
HIGH
t Rise time of both SDA and SCL signals
r
t Fall time of both SDA and SCL signals
f
Note: SCLL is also used to generate the
SCLH is also used to generate the
Refer to
I2C_TIMINGR settings vs. I2CCLK frequency.
Master communication initialization (address phase)
In order to initiate the communication, the user must program the following parameters for
the addressed slave in the I2C_CR2 register:
• Addressing mode (7-bit or 10-bit): ADD10
•
Slave address to be sent: SADD[9:0]
•
Transfer direction: RD_WRN
•
In case of 10-bit address read: HEAD10R bit. HEAD10R must be configure to indicate
if the complete address sequence must be sent, or only the header in case of a
direction change.
•
The number of bytes to be transferred: NBYTES[7:0]. If the number of bytes is equal to
or greater than 255 bytes, NBYTES[7:0] must initially be filled with 0xFF.
The user must then set the START bit in I2C_CR2 register. Changing all the above bits is
not allowed when START bit is set.
Then the master automatically sends the START condition followed by the slave address as
soon as it detects that the bus is free (BUSY = 0) and after a delay of t
In case of an arbitration loss, the master automatically switches back to slave mode and can
acknowledge its own address if it is addressed as a slave.
Note: The START bit is reset by hardware when the slave address has been sent on the bus,
whatever the received acknowledge value. The START bit is also reset by hardware if an
arbitration loss occurs.
In 10-bit addressing mode, when the Slave Address first 7 bits is NACKed by the slave, the
2
Table 228. I C-SMBus specification clock timings
Parameter
Section 34.4.10: I2C_TIMINGR register configuration examples
Inter-integrated circuit (I2C) interface
Standard- Fast-mode
mode (Sm) (Fm)
Min Max Min Max
- 100 -
4.0 - 0.6
4.7 - 0.6
4.0 - 0.6
4.7 - 1.3
4.7 - 1.3
4.0 - 0.6
- 1000 -
- 300 -
t and t timings.
BUF SU:STA
t and t timings.
HD:STA SU:STO
RM0453 Rev 2
Fast-mode
SMBus
Plus (Fm+)
Min Max Min
400 - 1000 -
- 0.26 - 4.0
- 0.26 - 4.7
- 0.26 - 4.0
- 0.5 - 4.7
- 0.5 - 4.7
- 0.26 - 4.0
300 - 120 -
300 - 120 -
for examples of
.
BUF
Unit
Max
100 kHz
- µs
- µs
- µs
- µs
- µs
50 µs
1000 ns
300 ns
1073/1454
1117