Figure 276. I2C Block Diagram - ST STM32WL55JC Reference Manual

RM0453
When the I2C is disabled (PE=0), the I
Section 34.4.6: Software reset
Noise filters
Before enabling the I2C peripheral by setting the PE bit in I2C_CR1 register, the user must
configure the noise filters, if needed. By default, an analog noise filter is present on the SDA
and SCL inputs. This analog filter is compliant with the I
suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The
user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by
configuring the DNF[3:0] bit in the I2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed
only if it remains stable for more than DNF x I2CCLK periods. This allows spikes with a
programmable length of 1 to 15 I2CCLK periods to be suppressed.
Pulse width of
suppressed spikes
Benefits
Drawbacks
Caution: Changing the filter configuration is not allowed when the I2C is enabled.
Table 225. Comparison of analog vs. digital filters
- Analog filter
≥ 50 ns
Available in Stop mode
Variation vs. temperature,
voltage, process
Inter-integrated circuit (I2C) interface
2
C performs a software reset. Refer to
for more details.
Programmable length from 1 to 15 I2C peripheral
clocks
– Programmable length: extra filtering capability
versus standard requirements
– Stable length
Wakeup from Stop mode on address match is not
available when digital filter is enabled
RM0453 Rev 2
2
C specification which requires the
Digital filter
1055/1454
1117