Figure 303. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1) - ST STM32WL55JC Reference Manual

Inter-integrated circuit (I2C) interface
Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP)
NBYTES
INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd PEC
Example SMBus master receiver 2 bytes + PEC, software end mode (RESTART)
INIT
NBYTES
xx
INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: read PEC
EV4: TC ISR: program Slave address, program NBYTES = N, set START
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Figure 304. Bus transfer diagrams for SMBus master receiver
data1
Address A
S
INIT
xx 3
RXNE
Address A data1 A
S
EV1
3
RXNE RXNE
PEC
data2
A A
E V 1 EV2
RXNE RXNE
data2 A PEC
NA
EV2 EV3
RM0453 Rev 2
RXNE
legend:
NA P
E V 3
legend:
TC
Restart Address
EV4
N
RM0453
transmission
reception
SCL stretch
transmission
reception
SCL stretch
MS19872V2