Embedded Flash memory (FLASH)
When at least one PES bit is set, the following occurs:
•
Any ongoing program or erase operation is completed.
The maximum latency for a Flash program erase suspension is the maximum time for
one program or erase operation to complete (see product datasheets for more
information on the Flash program and erase timing).
•
All new requested program and erase operations is not started but suspended.
PESD bits in FLASH_SR and FLASH_C2SR are set as soon as any PES is set, no
matter if a program/erase is currently suspended. This allows a CPU to test PESD prior
to requesting a program or an erase operation.
When all PES bits are reset to 0, a suspended program or erase operation is started: the
PESD bits are cleared.
4.8
FLASH interrupts
Interrupt event
End of operation
Operation error
Readout protection error
Write protection error
Size error
Programming sequential error
Programming alignment error
Programming sequence error
Data miss during fast programming error
Fast programming error
ECC error correction
ECC double-error (NMI)
1. EOP is set only if EOPIE is set.
2. OPERR is set only if ERRIE is set.
4.8.1
Illegal access interrupts
Unprivileged access to privileged registers generates an illegal access event. This event is
connected to the GTZC_TZIC.
Non-secure access to secure registers generates an illegal access event. This event is
connected to the GTZC_TZIC.
For more information on illegal access events see:
(GTZC).
126/1461
Table 23. Flash interrupt requests
Event flag
(1)
EOP
(2)
OPERR
RDERR
WRPERR
SIZERR
PROGERR
PGAERR
PGSERR
MISSERR
FASTERR
ECCC
ECCD
RM0453 Rev 1
Event flag/interrupt
clearing method
Write EOP=1
Write OPERR=1
Write RDERR=1
Write WRPERR=1
Write SIZERR=1
Write PROGERR=1
Write PGAERR=1
Write PGSERR=1
Write MISSERR=1
Write FASTERR=1
Write ECCC=1
Write ECCD=1
Section 3: Global security controller
RM0453
Interrupt enable
control bit
EOPIE
ERRIE
RDERRIE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ECCCIE
N/A
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