Hitachi SH7095 Hardware User Manual page 266

Figure 9.24 DACK Output in Synchronous DRAM Single Read (Bank Active, Same Row
Address, AM = 0)
Figure 9.25 DACK Output in Synchronous DRAM Single Read (Bank Active, Different
Row Address, AM = 0)
When external memory is set as bank active synchronous DRAM, during a write the acknowledge
signal is output across the wait and column address when the row address is the same as the
previous address output (figure 9.26). When the row address is different from the previous
address, the acknowledge signal is output across the precharge, row address, wait and column
address (figure 9.27).
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