Register Descriptions; Dma Source Address Registers 0 And 1 (Sar0 And Sar1) - Hitachi SH7095 Hardware User Manual

Table 9.2 DMAC Registers
Channel Name
0 DMA source address register 0 SAR0
DMA destination address
register 0
DMA transfer count register 0 TCR0
DMA channel control register 0 CHCR0
DMA vector number register
N0
DMA request/response
selection control register 0
1 DMA source address register 1 SAR1
DMA destination address
register 1
DMA transfer count register 1 TCR1
DMA channel control register 1 CHCR1
DMA vector number register
N1
DMA request/response
selection control register 1
Shared DMA operation register
Notes: 1. Writing permitted only when setting a 0 in bit 1 of CHCR0 and CHCR1 after reading 1 to
clear flags.
2. Writing permitted only when setting a 0 in bits 1 and 2 of the DMAOR after reading 1 to
clear flags.
3. Access DRCR0 and DRCR1 in byte units. Access all other registers in longword unit.
9.2

Register Descriptions

9.2.1

DMA Source Address Registers 0 and 1 (SAR0 and SAR1)

Bit:
Bit name:
Initial value:
R/W:
Abbr.
DAR0
VCRDMA0 R/(W)
DRCR0
DAR1
VCRDMA1 R/(W)
DRCR1
DMAOR
31 30
— —
R/W R/W R/W
Initial
R/W Value
R/W Undefined
R/W Undefined
R/W Undefined
*1
R/(W) H'00000000 H'FFFFFF8C
*1
Undefined
*1
R/(W) H'00
R/W Undefined
R/W Undefined
R/W Undefined
*1
R/(W) H'00000000 H'FFFFFF9C
*1
Undefined
*1
R/(W) H'00
*2
R/(W) H'00000000 H'FFFFFFB0
29 ...
...
— ... —
... R/W
Address
H'FFFFFF80
H'FFFFFF84
H'FFFFFF88
H'FFFFFFA0
H'FFFFFE71
H'FFFFFF90
H'FFFFFF94
H'FFFFFF98
H'FFFFFFA8
H'FFFFFE72
3 2
— —
R/W R/W
Access
*3
Size
32
32
32
32
32
*3
8
32
32
32
32
32
*3
8
32
1 0
—
R/W
Hitachi 225