Hitachi SH7095 Hardware User Manual page 494

Bit Bit Name
5 Overrun error (ORER)
4 Framing error (FER)
3 Parity error (PER)
2 Tranamit end (TEND)
1 Multiprocessor bit
(MPB)
0 Multiprocessor bit
transfer (MPBT)
Value
0 Receiving is in progress or has ended normally (initial
value).
ORER is cleared to 0 when the chip is reset or enters
standby mode or software reads ORER after it has been
set to 1, then writes 0 in ORER.
1 A receive overrun error occurred.
ORER is set to 1 if reception of the next serial data ends
when RDRF is set to 1.
0 Receiving is in progress or has ended normally (initial
value).
FER is cleared to 0 when the chip is reset or enters
standby mode or software reads FER after it has been
set to 1, then writes 0 in FER.
1 A receive framing error occurred.
FER is set to 1 if the stop bit at the end of receive data is
checked and found to be 0.
0 Receiving is in progress or has ended nomally (initial
value).
PER is cleared to 0 when the chip is reset or enters
standby mode or software reads PER after it has been
set to 1, then writes 0 in PER.
1 A receive parity error occurred.
PER is set to 1 if the number of ls in receive data,
including the parity bit, does not match the even or odd
parity setting of the parity mode bit (O/E) in the serial
mode register (SMR).
0 Transmission is in progress.
TEND is cleared to 0 when software reads TDRD after it
has been set to 1, then writing 0 in TDRE, or the DMAC
writes data in TDR.
1 End of transmission (initial value).
TEND is set to 1 when the chip is reset or enters standby
mode, TE is cleared to 0 in the serial control register
(SCR), or TDRE is 1 when the last bit of a one-byte serial
character is transmitted.
0 Multiprocessor bit value in receive data is 0 (initial value).
1 Multiprocessor bit value in receive data is 1.
0 Multiprocessor bit value in transmit data is 0 (initial
value).
1 Multiprocessor bit value in transmit data is 1.
SCI
Description
Hitachi 483