Hitachi SH7095 Hardware User Manual page 512

Break bus cycle register A
(BBRA)
Item 15
Bit name –
Initial Value 0
R/W R
Bit Bit Name
7, 6 CPU cycle/peripheral
cycle select A
(CPA1, CPA0)
5, 4 Instruction fetch/data
access select A
(IDA1, IDA0)
3, 2 Read/write select A
(RWA1, RWA0)
1, 0
Operand size select A
(SZA1, SZA0)
Break address register BH
(BARBH)
Item 15
Bit name BAB BAB
31
Initial Value 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 0 Break address BAB31-
BAB16
H'FFFFFF48
14 13 12 11
– – – –
0 0 0 0
R R R R
Value
0 0 No channel A user break interrupt occurs(initial value)
0 1 Break only on CPU cycles
1 0 Break only on peripheral cycles
1 1 Break on both CPU and peripheral cycles
0 0 No channel A user break interrupt occurs
0 1 Break only on instruction fetch cycles
1 0 Break only on data access cycles
1 1 Break on both instruction fetch and data access cycles
0 0 No channel A user break interrupt occurs
0 1 Break only on read cycles
1 0 Break only on write cycles
1 1 Break on both read and write cycles
0 0 Operand size is not a break condition
0 1 Break on byte access
1 0 Break on word access
1 1 Break on longword access
H'FFFFFF60
14 13 12 11
BAB BAB BAB
30 29 28 27
0 0 0 0
Bit nam
These bits specify the upper bits (bit 31 to bit 16) of the
address of the channel B break condition
Bit
10 9 8 7
– – – CPA
1
0 0 0 0
R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
10 9 8 7
BAB BAB BAB BAB
26 25 24 23
0 0 0 0
16/32
6 5 4 3
CPA IDA1 IDA0 RWA
0 1
0 0 0 0
Description
16/32
6 5 4 3
BAB BAB BAB BAB
22 21 20 19
0 0 0 0
Description
UBC
2 1 0
RWA SZA SZA
0 1 0
0 0 0
(initial value)
(initial value)
(initial value)
2 1 0
BAB BAB BAB
18 17 16
0 0 0
Hitachi 501