Hitachi SH7095 Hardware User Manual page 404

Table 15.5 Control Signal Timing (Conditions: V
(cont)
Item
BREQ delay time 1 (PLL on)
BACK setup time 1 (PLL on)
BACK hold time 1 (PLL on)
BREQ delay time 1 (PLL on, 1/4 cycle delay)
BACK setup time 1 (PLL on, 1/4 cycle delay)
BACK hold time 1 (PLL on, 1/4 cycle delay)
BREQ delay time 2 (PLL on)
BACK setup time 2 (PLL on)
BACK hold time 2 (PLL on)
Bus tri-state delay time 1 (PLL on)
Bus buffer on time 1 (PLL on)
Bus tri-state delay time 1 (PLL on, 1/4 cycle delay) t
Bus buffer on time 1 (PLL on, 1/4 cycle delay)
Bus tri-state delay time 1 (PLL off)
Bus buffer on time 1 (PLL off)
Bus tri-state delay time 2 (PLL on)
Bus buffer on time 2 (PLL on)
Bus tri-state delay time 2 (PLL on, 1/4 cycle delay) t
Bus buffer on time 2 (PLL on, 1/4 cycle delay)
Bus tri-state delay time 3 (PLL off)
Bus buffer on time 3 (PLL off)
= 5.0 V ±10%, Ta = -20 to +75°C)
CC
Symbol Min
t —
BRQD1
t 1/2 tcyc + 9 —
BAKS1
t 9 – 1/2 tcyc 28
BAKH1
t —
BRQD1
t 1/4t cyc + 9 —
BAKS1
t 9 – 1/4 tcyc 28
BAKH1
t —
BRQD2
t 9
BAKS2
t 19
BAKH2
t 0
BOFF1
t 0
BON1
1/4 tcyc
BOFF1
t 1/4 tcyc
BON1
t 0
BOFF1
t 0
BON1
t 1/2 tcyc
BOFF2
t 1/2 tcyc
BON2
3/4 tcyc
BOFF2
t 3/4 tcyc
BON2
t 0
BOFF3
t 0
BON3
Max Unit Figure
1/2 tcyc +18 ns 15.12
ns
ns
3/4 tcyc +18 ns 15.12
ns
ns
28 ns 15.13
— ns
— ns
25 ns 15.10,
15.12
18 ns
1/4 tcyc + 25 ns 15.10,
15.12
1/4 tcyc + 18 ns
30 ns 15.11,
15.13
25 ns
1/2 tcyc + 25 ns 15.10,
15.12
1/2 tcyc + 18 ns
3/4 tcyc + 25 ns 15.10,
15.12
3/4 tcyc + 18 ns
30 ns 15.11,
15.13
25 ns
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