Hitachi SH7095 Hardware User Manual page 496

Timer interrupt enable register
(TIER)
Item 7
Name ICIE
Initial Value 0
R/W R/W
Bit Bit Name
7 Input capture interrupt
enable (ICIE)
3 Output compare
interrupt A enable
(OCIAE)
2 Output compare
interrupt B enable
(OCIBE)
1 Timer overflow interrupt
enable (DVIE)
Free-running timer control/status
register (FTCSR)
Item 7
Bit Name ICF
Initial Value 0
R/W R/(W)*
Note : For bits 7, and 3 to 1, the only value that can be written is 0 (for clearing the flags)
Bit Bit Name
7 Input capture flag (ICF)
3 Output compare flag A
(OCFA)
H'FFFFFE10
6 5
– –
0 0
R/W R/W
Value
0 Disables interrupt requests (ICI) from the ICF (initial
value)
1 Enables interrupt requests (ICI) from the ICF
0 Disables interrupt requests (OCIA) from the OCFA (initial
value)
1 Enables interrupt requests (OCIA) from the OCFA
0 Disables interrupt requests (OCIB) from the OCFB (initial
value)
1 Enables interrupt requests (OCIB) from the OCFB
0 Disables interrupt requests (OVI) from the OVF (initial
value)
1 Enables interrupt requests (OVI) from the OVF
H'FFFFFE11
6 5
– –
0 0
– –
Value
0 Clear conditions: When ICF = 1, ICF is read and then 0 is
written to it (initial value)
1 Set conditions: When FRC value is sent to the ICR by the
input capture signal
0 Clear conditions: When OCFA = 1, OCFA is read and
then 0 is written to it (initial value)
1 Set conditions: When FRC value becomes equal to
OCRA
8
Bit
4 3
– OCIAE OCIBE
0 0
R/W R/W
Description
8
Bit
4 3
– OCFA
0 0
– R/(W)*
Description
FRT
2 1
OVIE
0 0
R/W R/W
2 1
OCFB OVF
0 0
R/(W)* R/(W)*
Hitachi 485
0
–
1
R/W
0
CCLRA
0
R/W