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Table 2.17 lists the minimum execution cycles. In practice, the number of execution cycles
increases when the instruction fetch is in contention with data access or when the destination
register of a load instruction (memory → register) is the same as the register used by the next
instruction.
Table 2.17 System Control Instructions
Instruction
CLRT
CLRMAC
LDC
Rm,SR
LDC
Rm,GBR
LDC
Rm,VBR
LDC.L
@Rm+,SR
LDC.L
@Rm+,GBR
LDC.L
@Rm+,VBR
LDS
Rm,MACH
LDS
Rm,MACL
LDS
Rm,PR
LDS.L
@Rm+,MACH
LDS.L
@Rm+,MACL
LDS.L
@Rm+,PR
NOP
RTE
SETT
SLEEP
STC
SR,Rn
STC
GBR,Rn
STC
VBR,Rn
STC.L
SR,@–Rn
STC.L
GBR,@–Rn
STC.L
VBR,@–Rn
Hitachi 38
Instruction Code
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000000101011
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
Operation
0 → T
0 → MACH, MACL
Rm → SR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm 3
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 →
Rm
(Rm) → MACL, Rm + 4 →
Rm
(Rm) → PR, Rm + 4 → Rm
No operation
Delayed branch, stack area
→ PC/SR
1 → T
Sleep
SR → Rn
GBR → Rn
VBR → Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
Rn–4 → Rn, VBR → (Rn)
Execu-
tion
T
Cycles
Bit
1
0
1
—
1
LSB
1
—
1
—
3
LSB
—
3
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
4
—
1
1
*
3
—
1
—
1
—
1
—
2
—
2
—
2
—
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