Register Descriptions; Free-Running Counter (Frc); Output Compare Registers A And B (Ocra And Ocrb) - Hitachi SH7095 Hardware User Manual

11.2

Register Descriptions

11.2.1

Free-Running Counter (FRC)

Bit:
Bit name:
Initial value:
R/W:
The FRC is a 16-bit read/write up-counter. It increments upon input of a clock. The input clock
can be selected using clock select bits 1 and 0 (CKS1, CKS0) of the TCR. The FRC can be cleared
upon compare match A.
When the FRC overflows (H'FFFF → H'0000), the overflow flag (OVF) of the FTCSR is set to 1.
The FRC can be read or written to by the CPU, but because it is 16 bits, data transfers involving
the CPU go through a temporary register (TEMP). See section 11.3, CPU Interface, for more
detailed information.
The FRC is initialized to H'0000 by a reset, in the standby mode, and when the module standby
function is used.
11.2.2

Output Compare Registers A and B (OCRA and OCRB)

Bit:
Bit name:
Initial value:
R/W:
The OCR is composed of two 16-bit read/write registers (OCRA and OCRB). The contents of the
OCR are always compared to the FRC value. When the two values are the same, the output
compare flags of the FTCSR (OCFA and OCFB) are set to 1.
When the OCR values and FRC values are the same (compare match), the output level values set
in the output level bits (OLVLA and OLVLB) are output to the output compare pins (FTOA and
FTOB). After a reset, FTOA and FTOB output 0 until the first compare match occurs.
Because the OCR is a 16-bit register, data transfers involving the CPU go through a temporary
register (TEMP). See section 11.3, CPU Interface, for more detailed information.
The OCR is initialized to H'FFFF by a reset, in the standby mode, and when the module standby
function is used.
288 Hitachi
15 14
0 0
R/W R/W R/W
15 14
1 1
R/W R/W R/W
13 ...
...
0 ...
... R/W
13 ...
...
1 ...
... R/W
3 2
0 0
R/W R/W
3 2
1 1
R/W R/W
1 0
0 0
R/W
1 0
1 1
R/W