Hitachi SH7095 Hardware User Manual page 411

Table 15.7 Bus Timing With PLL On and 1/4 Cycle Delay (Conditions: V
Ta = -20 to +75°C)
Item
Address delay time
BS delay time
CS delay time 1
CS delay time 2
Read write delay time
Read strobe delay time 1
Read data setup time 1
Read data setup time 3
(SDRAM)
Read data hold time 2
Read data hold time 4
(SDRAM)
Read data hold time 5
(DRAM)
Read data hold time 6
(PSRAM)
Read data hold time 7
(interrupt vector)
Write enable delay time
Write data delay time 1
Write data hold time 1
Data buffer on time
Data buffer off time
400 Hitachi
Symbol Min
t 1/4 tcyc + 3
AD
t —
BSD
t —
CSD1
—
t
CSD2
t 1/4 tcyc + 3
RWD
t —
RSD1
t 1/4 tcyc + 10 —
RDS1
t 1/4 tcyc + 8
RDS3
t 0
RDH2
t 0
RDH4
t 0
RDH5
t 0
RDH6
t 0
RDH7
t 3/4 tcyc + 3
WED1
t 1/4 tcyc + 3
WDD
t 1/4 tcyc + 3
WDH1
t —
DON
t —
DOF
Max Unit Figures
1/4 tcyc + 18 ns
1/4 tcyc + 21 ns
1/4 tcyc + 21 ns
3/4 tcyc + 21 ns
1/4 tcyc + 18 ns
3/4 tcyc + 16 ns
ns
— ns
— ns
— ns
— ns
— ns
— ns
3/4 tcyc + 18 ns
1/4 tcyc + 18 ns
— ns
1/4 tcyc + 18 ns
1/4 tcyc + 18 ns
= 5.0 V ±10%,
CC
15.14, 15.20, 15.40,
15.52, 15.66, 15.68
15.14, 15.20, 15.40,
15.52, 15.66
15.14, 15.20, 15.40,
15.52, 15.66
15.14, 15.66
15.14, 15.20, 15.40,
15.52, 15.66
15.14, 15.40, 15.52,
15.66, 15.68
15.14, 15.40, 15.52,
15.66, 15.68
15.20
15.14, 15.66
15.20
15.40
15.52
15.68
15.14, 15.15, 15.52,
15.53
15.15, 15.27, 15.41,
15.53
15.15, 15.27, 15.41,
15.53
15.15, 15.27, 15.41,
15.53
15.15, 15.27, 15.41,
15.53