Hitachi SH7095 Hardware User Manual page 5

5.3.2 Interrupt Priority Level Setting Register B (IPRB) ......................................
5.3.3 Vector Number Setting Register WDT (VCRWDT) ....................................
5.3.4 Vector Number Setting Register A (VCRA) ..............................................
5.3.5 Vector Number Setting Register B (VCRB)...............................................
5.3.6 Vector Number Setting Register C (VCRC)...............................................
5.3.7 Vector Number Setting Register D (VCRD) ..............................................
5.3.8 Interrupt Control Register (ICR)..............................................................
5.4 Interrupt Operation ..........................................................................................
5.4.1 Interrupt Sequence................................................................................
5.4.2 Stack after Interrupt Exception Processing................................................. 87
5.5 Interrupt Response Time...................................................................................
5.6 Sampling of the IRL Pins (0-3)..........................................................................
5.7 Notes on Use ..................................................................................................
Section 6 User Break Controller
6.1 Overview.......................................................................................................
6.1.1 Features..............................................................................................
6.1.2 Block Diagram..................................................................................... 96
6.1.3 Register Configuration ..........................................................................
6.2 Register Descriptions .......................................................................................
6.2.1 Break Address Register A (BARA)..........................................................
6.2.2 Break Address Mask Register A (BAMRA)............................................... 99
6.2.3 Break Bus Cycle Register A (BBRA) ....................................................... 100
6.2.4 Break Address Register B (BARB) .......................................................... 102
6.2.5 Break Address Mask Register B (BAMRB)............................................... 102
6.2.6 Break Data Register B (BDRB)............................................................... 102
6.2.7 Break Data Mask Register B (BDMRB).................................................... 103
6.2.8 Bus Break Register B (BBRB) ................................................................ 104
6.2.9 Break Control Register (BRCR) .............................................................. 105
6.3 Operation....................................................................................................... 108
6.3.1 Flow of the User Break Operation............................................................ 108
6.3.2 Break on Instruction Fetch Cycle............................................................. 109
6.3.3 Break on Data Access Cycle................................................................... 109
6.3.4 Break on External Bus Cycle .................................................................. 110
6.3.5 Program Counter (PC) Values Saved........................................................ 110
6.3.6 Use Examples...................................................................................... 111
6.3.7 Notes on Use ....................................................................................... 113
6.3.8 SH7000-Series Compatibility Mode......................................................... 114
Section 7 Bus State Controller (BSC)
7.1 Overview....................................................................................................... 117
7.1.1 Features.............................................................................................. 117
7.1.2 Block Diagram..................................................................................... 118
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