Power-On Sequence - Hitachi SH7095 Hardware User Manual

when the two match, starting a CAS-before-RAS refresh. RTCNT is cleared to 0 at that time and
the count up starts up again. Figure 7.35 shows the timing for the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified in the TRAS bit of the MCR. As
with ordinary accesses, the specification of the RAS precharge time in refresh cycles follows the
TRP bit of the MCR.
Figure 7.35 Refresh Cycle Timing
7.6.7

Power-On Sequence

When DRAM is being used after the power is turned on, dummy CAS-before-RAS refresh cycles
longer than the waiting time during which accesses cannot be performed (100 µs or 200 µs
minimum) and a prescribed number that follows it (usually 8) are requested. The bus state
controller does not perform any special operations for the power-on reset, so the required power-
on sequence must be implemented by the initialization program executed after a power-on reset.
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