Hitachi SH7095 Hardware User Manual page 173

Figure 7.25 Auto-Refresh Timing
Self-Refreshes: The self-refresh mode is a type of standby mode that produces refresh timing and
refresh addresses within the synchronous DRAM. It is started up by setting the RMODE and
RFSH bits to 1. The synchronous DRAM is in self-refresh mode when the CKE signal level is
low. During the self refresh, the synchronous DRAM cannot be accessed. To clear the self refresh,
set the RMODE bit to 0. After self-refresh mode is cleared, issuing of commands is prohibited for
the number of cycles specified in the MCR's TRAS bit + 1 cycle. Figure 7.26 shows the self-
refresh timing. Immediately set the synchronous DRAM so that the auto refresh is performed in
the correct interval. This ensures a correct self-refresh clear and data holding. When self refresh is
entered while the synchronous DRAM is set for auto refresh or when leaving the standby mode
with a manual reset or NMI, auto refresh can be re-started if the RFSH is 1 and RMODE is 0 when
the self-refresh mode is cleared. When time is required between clearing the self-refresh mode and
starting the auto-refresh mode, this time must be reflected in the initial RTCNT setting. When the
RTCNT value is set to RTCOR – 1, the refresh can be started immediately.
If the standby function of the SH7095 is used after the self refresh is set to enter the standby mode,
the self-refresh state continues; the self-refresh state will also be maintained after returning from a
standby using an NMI.
Manual reset cannot be used to get out of self refresh either. During a power-on reset, the bus state
controller register is initialized, so the self-refresh state is ended.
Refresh Requests and Bus Cycle Requests: When a refresh request occurs while a bus cycle is
executing, the refresh will not be executed until the bus cycle is completed. When a refresh request
occurs while the bus is released using the bus arbitration function, the refresh will not be executed
until the bus is recaptured. If RTCNT and RTCOR match and a new refresh request occurs while
waiting for the refresh to execute, the previous refresh request is erased. To make sure the refresh
executes properly, be sure that the bus cycle and bus capture do not exceed the refresh interval.
If a bus arbitration request occurs during a self refresh, the bus is not released until the self refresh
is cleared. During self refresh, the slave chips halt if there is a master-slave structure.
162 Hitachi