Vector Number Setting Register (Vcrdiv); Dividend Register H (Dvdnth) - Hitachi SH7095 Hardware User Manual

10.2.4

Vector Number Setting Register (VCRDIV)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
The vector number setting register (VCRDIV) is a 32-bit read/write register, but is also 16-bit
accessible. Interrupt destination vector numbers are set in VCRDIV when an interrupt occurs in
the division unit due to an overflow or underflow. Values can be set in the 16 bits from bit 15 to
bit 0, but only the last 7 bits (bits 6–0) are valid. Always set 0 for the 9 bits from bit 15 to bit 7. It
is not initialized by power-on resets, manual resets, in the standby mode and in the module
standby mode.
• Bits 31 to 7: Reserved. These bits cannot be modified and always read 0.
• Bits 6 to 0: Interrupt vector numbers. Sets the interrupt destination vector number. Only bits
6–0 are valid (7 bits).
10.2.5

Dividend Register H (DVDNTH)

Bit:
Bit name:
Initial value:
R/W:
The dividend register H (DVDNTH) is a 32-bit read/write register in which the upper 32 bits of
the dividend used for 64 bit / 32 bit division operations are written. When a division operation is
executed, the value set as the dividend is lost and the remainder written here at the end of the
operation. The initial value of the DVDNTH is undefined and are undefined after a power-on
reset, manual reset, in the standby mode, or in the module standby mode. When the DVDNT
register is set with a dividend value, the previous DVDNTH value is lost and the MSB of the
DVDNT register is expanded to the entire DVDNTH.
31 30
— —
0 0
R R
15 14
— —
R/W R/W R/W
31 30
— —
R/W R/W R/W
29 ... 19
— ... —
0 ...
R ...
13 ...
...
— ... —
... R/W
39 ...
...
— ... —
... R/W
18 17
— —
0 0
R R
3 2
— —
R/W R/W
3 2
— —
R/W R/W
16
—
0 0
R R
1 0
—
R/W
1 0
—
R/W
Hitachi 281