Hitachi SH7095 Hardware User Manual page 29

Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are
executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation
operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit and 32-bit × 32-bit + 64bit
→ 64-bit multiplication/accumulation operations are executed in two to four cycles.
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch (table 2.4). The number
of instructions after the T bit in the status register is kept to a minimum to improve the processing
speed.
Table 2.4 T Bit
SH7095 Series CPU
CMP/GE R1,R0
BT TRGET0
BF TRGET1
ADD #–1,R0
CMP/EQ #0,R0
BT TRGET
Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate
data is not input via instruction codes but is stored in a memory table. An immediate data transfer
instruction (MOV) accesses the memory table using the PC relative addressing mode with
displacement (table 2.5).
Table 2.5 Immediate Data Accessing
Classification
8-bit immediate
16-bit immediate
32-bit immediate
Note: @(disp, PC) accesses the address of the immediate data.
Absolute Address: When data is accessed by absolute address, the value already in the absolute
address is placed in the memory table. Loading the immediate data when the instruction is
Hitachi 18
Description
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD. T bit is
set when R0 = 0. The program
branches if R0 = 0.
SH7095 Series CPU
MOV #H'12,R0
MOV.W @(disp,PC),R0
.................
.DATA.W H'1234
MOV.L @(disp,PC),R0
.................
.DATA.L H'12345678
Example of Conventional CPU
CMP.W R1,R0
BGE TRGET0
BLT TRGET1
SUB.W #1,R0
BEQ TRGET
Example of Conventional CPU
MOV.B #H'12,R0
MOV.W #H'1234,R0
MOV.L #H'12345678,R0