Dma Request/Response Selection Control Registers 0 And 1 (Drcr0, Drcr1) - Hitachi SH7095 Hardware User Manual

• Bits 7–0—Vector Number Bits 7–0 (VC7–VC0): Set the interrupt vector numbers at the end
of a DMAC transfer. Interrupt vector numbers of 0–127 can be set. When a transfer-end
interrupt occurs, exception processing and interrupt control fetch the vector number and
control is transferred to the specified interrupt processing routine. The VC7–VC0 bits become
undefined upon reset or in the standby mode. Always write 0 to VC7.
9.2.6

DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1)

Bit:
Bit name:
Initial value:
R/W:
The DMA request/response selection control registers 0 and 1 (DRCR0, DRCR1) are 8-bit
read/write registers that set the vector address of the DMAC transfer request source. It is written as
an 8-bit value. It is initialized to H'00 by a reset. It holds the value in the module standby.
• Bits 7–2—Reserved: These bits cannot be modified. They always read 0.
• Bits 1, 0—Resource Select Bits 1,0 (RS1, RS0): Specify which transfer request to input to the
DMAC. Changing the transfer request source must be done when the DMA enable bit (DE) is
0. The RS1 and RS0 bits are initialized to H'00 by a reset.
Bit 1: RS1 Bit 0: RS0
0 0
0 1
1 0
1 1
Note: For RX2 and TX1, set for dual transfer mode.
The DREQ settings in the CHCR are DS = 1 and DL = 0.
232 Hitachi
7 6
— — —
0 0
R R
Description
DREQ (external request) (initial value)
RXI (receive-data-full interrupt transfer request of the on-chip
serial communication interface (SCI))*
TXI (transmit-data-empty interrupt transfer request of the on-
chip SCI)*
Reserved (setting disabled)
5 4 3
— —
0 0 0
R R R
2 1
— RS1 RS0
0 0
R R/W R/W
0
0