Hitachi SH7095 Hardware User Manual page 529

BSC
Refresh timer control/status
register (RTCSR)
Item 15 14
Bit Name – –
Initial Value 0 0
R/W R R
Bit Bit Name
7 Compare match flag
(CMF)
6 Compare match
interrupt enable (CMIE)
5 t0 3 Clock select bits
(CKS2-CKS0)
Refresh timer counter (RTCNT)
Item 15 14
Bit Name – –
Initial Value 0 0
R/W R R
Bit
7 to 0 (count value)
Refresh time constant register
(RTCOR)
Item 15 14
Bit Name – –
Initial Value
0 0
R/W R R
Bit
7 to 0 (Timer constant)
518 Hitachi
H'FFFFFFF0
13 12 11
– – –
0 0 0
R R R
Value
–
0
1
0 0 0 Disables count up (initialal value)
0 0 1 CLK/4
0 1 0 CLK/16
0 1 1 CLK/64
1 0 0 CLK/256
1 0 1 CLK/1024
1 1 0 CLK/2048
1 1 1 CLK/4096
H'FFFFFFF4
13 12 11
– – –
0 0 0
R R R
Bit Name
H'FFFFFFF8
13 12 11
– – –
0 0 0
R R R
Bit Name
Bit
10 9 8 7
– – – CMF CMI
0 0 0 0
R R R R/W R/W R/W R/W R/W
RTCNT and RTCOR match
Clear condition: After RTCSR is read when CMF is 1, O
is written in CMF
Disables an interrupt request caused by CMF (initial
value)
Enables an interrupt request caused by CMF
Bit
10 9 8 7
– – –
0 0 0 0
R R R R/W R/W R/W R/W R/W R/W R/W R/W
Input clock count value
Bit
10 9 8 7
– – –
0 0 0 0
R R R R/W R/W R/W R/W R/W R/W R/W R/W
Sets the refresh cycle
16/32
6 5 4 3
CKS2 CKS1 CKS0 –
E
0 0 0 0
Description
16/32
6 5 4 3
0 0 0 0
Description
16/32
6 5 4 3
0 0 0 0
Description
2 1 0
– –
0 0 0
R R R
2 1 0
0 0 0
2 1 0
0 0 0