Hitachi SH7095 Hardware User Manual page 377

2. To continue transmitting serial data. read the TDRE bit to check whether it is safe to write (if
it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a
transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked
and cleared automatically.
Figure 13.17 Sample Flowchart for Serial Transmitting
Receiving Serial Data (Clocked Synchronous Mode): Figure 13.18 shows a sample flowchart
for receiving serial data. When switching from the asynchronous mode to the clocked synchronous
mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF
bit will not be set and both transmitting and receiving will be disabled. Figure 13.19 shows an
example of the SCI receive operation.
The procedure for receiving serial data is listed below:
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