Hitachi SH7095 Hardware User Manual page 143

• Bit 9—RAS Down Mode (RASD): Bank active mode.
Bit 9 (RASD)
0
1
• Bits 7, 5, and 4—Address Multiplex (AMX2–AMX0): For DRAM interface:
Bit 7 Bit 5
(AMX2) (AMX1)
0 0
1
1 0
1
For synchronous DRAM interface:
Bit 7 Bit 5
(AMX2) (AMX1)
0 0
1
1 0
1
Note: Reserved. Do not set when SZ bit in MCR is 0 (16-bit bus width).
132 Hitachi
Description
For synchronous DRAM, read or write is performed using auto-
precharge mode. The next access always starts with bank active
commands.
For synchronous DRAM, access ends with bank active status. This is
only valid for area 3. When area 2 is synchronous DRAM, the mode is
always auto precharge.
Bit 4
(AMX0)
0
1
0
1
0
1
0
1
Bit 4
(AMX0)
0
1
0
1
0
1
0
1
Description
8-bit column address DRAM
9-bit column address DRAM
10-bit column address DRAM
11-bit column address DRAM
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
Description
16-Mbit DRAM (1M × 16 bits)
16-Mbit DRAM (2M × 8 bits)*
16-Mbit DRAM (4M × 4 bits)*
4-Mbit DRAM (256k × 16 bits)
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
2-Mbit DRAM (128k × 16 bits)