Break Address Mask Register A (Bamra) - Hitachi SH7095 Hardware User Manual

• BARAL Bits 15 to 0—Break Address A 15 to 0 (BAA15 to BAA0): These bits store the
lower bit values (bits 15 to 0) of the address of the channel A break condition.
6.2.2

Break Address Mask Register A (BAMRA)

BAMRAH:
Bit:
Bit name: BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24
Initial value:
R/W:
Bit:
Bit name: BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16
Initial value:
R/W:
BAMRAL:
Bit:
Bit name: BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8
Initial value:
R/W:
Bit:
Bit name: BAMA7
Initial value:
R/W:
The two break address mask registers A (BAMRA)—break address mask register AH
(BAMRAH) and break address mask register AL (BAMRAL)—together form a single group.
Both are 16-bit read/write registers. BAMRAH determines which of the bits in the break address
set in BARAH are masked. BAMRAL determines which of the bits in the break address set in
BARAL are masked. A power-on reset initializes BAMRAH and BAMRAL to H'0000.
• BAMRAH Bits 15 to 0—Break Address Mask A 31 to 16 (BAMA31 to BAMA16): These
bits specify whether bits 31–16 (BAA31 to BAA16) of the channel A break address set in
BARAH are masked or not.
15 14
0 0
R/W R/W R/W
7 6
0 0
R/W R/W R/W
15 14
0 0
R/W R/W R/W
7 6
BAMA6 BAMA5
0 0
R/W R/W R/W
13 12 11
0 0
R/W R/W
5 4
0 0
R/W R/W
13 12 11
0 0
R/W R/W
5 4
BAMA4 BAMA3
0 0
R/W R/W
10
0 0
R/W R/W
3 2
0 0
R/W R/W
10
0 0
R/W R/W
3 2
BAMA2 BAMA1 BAMA0
0 0
R/W R/W
9 8
0 0
R/W
1 0
0 0
R/W
9 8
0 0
R/W
1 0
0 0
R/W
Hitachi 99