Hitachi SH7095 Hardware User Manual page 256

In the dual address mode transfers, external memory, memory-mapped external devices and
on-chip peripheral modules can be mixed without restriction. Specifically, this enables
transfers between the following:
1. External memory and external memory.
2. External memory and memory-mapped external devices.
3. Memory-mapped external devices and memory-mapped external devices.
4. External memory and on-chip peripheral modules (excluding the DMAC, BSC, and
UBC).
5. Memory-mapped external devices and on-chip peripheral modules (excluding the
DMAC, BSC, and UBC). Access size that is enabled by the register of the on-chip
peripheral module that is the source or destination (excludes DMAC, BSC, and UBC).
6. On-chip peripheral modules (excluding the DMAC, BSC, and UBC) and on-chip
peripheral modules (excluding the DMAC, BSC, and UBC).
Transfer requests can be auto-requests, external requests, or on-chip peripheral module
requests. When the transfer request source is the SCI, however, either the data destination or
source must be the SCI (see table 9.6). The dual address mode outputs the DACK in either the
read cycle or write cycle. The CHCR controls the cycle of DACK output.
Figure 9.9 shows the DMA transfer timing in the dual address mode.
Figure 9.8 Data Flow in the Dual Address Mode
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