Hitachi SH7095 Hardware User Manual page 172

Auto Refresh: Refreshes are performed at the interval determined by the input clock selected by
the CKS2–CKS0 bits of the RTCSR and the value set in RTCOR. Set the CKS2–CKS0 bits and
RTCOR so that the refresh interval specifications of the synchronous DRAM being used are
satisfied. First, set the RTCOR, RTCNT and the RMODE and RFSH bits of the MCR, then set the
CKS2–CKS0 bits. When a clock is selected with the CKS2–CKS0 bits, RTCNT starts counting up
from the value at that time. The RTCNT value is constantly compared to the RTCOR value and a
request for a refresh is made when the two match, starting an auto refresh. RTCNT is cleared to 0
at that time and the count up starts up again. Figure 7.25 shows the timing for the auto-refresh
cycle.
First, a PALL command is issued during the Tp cycle to change all the banks from active to
precharge states. A REF command is then issued in the Trr cycle. After the Trr cycle, no new
commands are output for the number of cycles specified in the TRAS bit of the MCR + 2 cycles.
The TRAS bit must be set to satisfy the refresh cycle time specifications (active/active command
delay time) of the synchronous DRAM. When the MCR's TRP bit is 1, an NOP cycle is inserted
between the Tp cycle and Trr cycle.
During a manual reset, no refresh request is occurred, since there is no RTCNT count-up. To
perform a refresh properly, make the manual reset period shorter than the refresh cycle interval
and set RTCNT to (RTCOR – 1) so that the refresh is performed immediately after the manual
reset is cleared.
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