Hitachi SH7095 Hardware User Manual page 136

• Bit 11—Area 0 Burst ROM Enable (BSTROM)
Bit 11 (BSTROM)
0
1
• Bit 10—Partial Space Share Specification (PSHR): When bus arbitration is in master mode
and the PSHR bit is 1, only area 2 is handled as a shared space. When areas other than area 2
are accessed, bus ownership is not requested. When this bit is 1, address monitor specification
is disabled. This mode is called partial-share master mode. The initial value is 0.
• Bits 9–8—Long Wait Specification of Areas 2 and 3 (AHLW1–AHLW0): When the basic
memory interface settings are area 2 and area 3, the wait specifications of these fields are
effective when the bits that specify the respective area waits in the wait control registers
(W21/W20 and W31/W30) specify long waits (i.e., 11).
Bit 9 (AHLW1) Bit 8 (AHLW0)
0 0
1
1 0
1
• Bits 7–6—Long Wait Specification of Area 1 (A1LW1–A1LW0): When the basic memory
interface setting is area 1, the wait specifications of these fields are effective when the bit that
specifies the wait in the wait control registers specifies long wait (i.e., 11).
Bit 7 (A1LW1) Bit 6 (A1LW0)
0 0
1
1 0
1
• Bits 5–4—Long Wait Specification of Area 0 (A0LW1–A0LW0): When the basic memory
interface setting is area 0, the wait specifications of these fields are effective when the bit that
specifies the wait in the wait control registers specifies long wait (i.e., 11).
Description
Area 0 is accessed normally (Initial value)
Area 0 is accessed as burst ROM
Description
3 waits
4 waits
5 waits
6 waits (Initial value)
Description
3 waits
4 waits
5 waits
6 waits (Initial value)
Hitachi 125