Register Configuration - Hitachi SH7095 Hardware User Manual

Table 7.1 Pin Configuration (cont)
With Bus
Signal I/O Released
O Hi-Z
CASLH,
DQMLU,
WE1
O Hi-Z
CASLL,
DQMLL,
WE0
O Hi-Z
RD
I Ignore
WAIT
I I
BACK,
BRLS
BREQ, O O
BGR
CKE O O
O Hi-Z
IVECF
DREQ0 I I
DACK0 O O
DREQ1 I I
DACK1 O O
Note: Hi-Z: High impedance
7.1.4

Register Configuration

The BSC has seven registers. These registers are used to control wait states, bus width, and
interfaces with memories like DRAMs, synchronous DRAMs, pseudo SRAMs, burst ROM,
DRAM, synchronous DRAM, and pseudo SRAM refreshes. The register configurations are listed
in table 7.2.
The size of the registers themselves is 16 bits. If read as 32 bits, the top 16 bits are 0. In order to
prevent writing mistakes, 32-bit writes are accepted only when the top 16 bits of write data is
H'A55A; no other writes are performed. Initialize the reserved bits.
Description
When DRAM is used, connected to CAS pin for the third byte
(D15–D8). When synchronous DRAM is used, connected to DQM
pin for the third byte. When pseudo SRAM is used, connected to
WE pin for the third byte. For basic interface, indicates writing to
the third byte.
When DRAM is used, connected to CAS pin for the least significant
byte (D7–D0). When synchronous DRAM is used, connected to
DQM pin for the least significant byte. When pseudo SRAM is
used, connected to WE pin for the least significant byte. For basic
interface, indicates writing to the least significant byte.
Read pulse signal (read data output enable signal). Normally,
connected to the device's /OE pin; when there is an external data
buffer, the read cycle data can only be output when this signal is
low.
Hardware wait input.
Bus use enable input in partial master or slave: BACK. Bus release
request input in total master: BRLS.
Bus request output in partial master or slave: BREQ. Bus grant
output in total master: BGR.
Synchronous DRAM clock enable control. Signal for supporting
synchronous DRAM self refresh.
Interrupt vector fetch.
DMA request 0.
DMA acknowledge 0.
DMA request 1.
DMA acknowledge 1.
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