Hitachi SH7095 Hardware User Manual page 315

1. The FRC operates at the timer drive clock (φ/4), which has a cycle of 4 times the system clock
(φ). For this reason, when the CPU is accessed, both the CPU and FRT will be operating, so a
WAIT request will be generated from the FRT to the CPU. The number of access cycles is
thus changed by between 3 and 12 cycles.
2. Contention between FRC Writes and Clears
When a counter clear signal is generated with the timing shown in figure 11.14 during the
write cycle for the lower byte of the FRC, writing does not occur to the FRC, and the FRC
clear takes priority.
Figure 11.14 Contention between FRC Write and Clear
3. Contention between FRC Writes and Increments
When an increment occurs with the timing shown in figure 11.15 during the write cycle for
the lower byte of the FRC, no increment is performed and the counter write takes priority.
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