Hitachi SH7095 Hardware User Manual page 177

the synchronous DRAM access time. When a clock system is connected without a means of
synchronization such as an on-chip PLL, transmission from the SH7095 to the synchronous
DRAM takes 1 cycle less the delay time of the clock system and transmission from the
synchronous DRAM to the SH7095 takes 1/2 cycle plus the clock system delay time. The clock
system delay time changes with the power supply voltage, temperature, and manufacturing
variance, so it has a fairly wide range. When the phase of the internal clock of the SH7095 is
delayed using a PLL that delays the phase 90 degrees relative to external clocks, transmission
from the SH7095 to the synchronous DRAM and transmission from the SH7095 to the
synchronous DRAM each takes 3/4 cycle.
Given this, using a clock whose phase is shifted 90 degrees from the external clock using a PLL as
the internal clock can ensure a margin of safety.
When using a PLL, it is important to note that the synchronous DRAM does not contain an on-
chip PLL. When using the external clock input clock mode, instability in the clock supplied from
outside can cause shifts in phase, so a synchronization settling time in the SH7095's on-chip PLL
is needed to equalize the SH7095's internal clock and the external clock. During this
synchronization settling time, the internal clock of the synchronous DRAM and the internal clock
of the SH7095 will not always operate in perfect synchronization. To ensure the synchronous
DRAM and SH7095 operate properly, be sure that the external clock supplied is not unstable.
166 Hitachi