Individual Memory Control Register (Mcr) - Hitachi SH7095 Hardware User Manual

7.2.4

Individual Memory Control Register (MCR)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
The TRP, RCD, TRWL, TRAS1–TRAS0, BE, RASD, AMX2–AMX0 and SZ bits are initialized
after a power-on reset. Do not write to them thereafter. When writing to them, write the same bits
they are initialized to. Do not access any space other than CS2 and CS3 until the register
initialization ends.
• Bit 15—RAS Precharge Time (TRP): When DRAM is connected, specifies the minimum
number of cycles after RAS is negated before next assert. When pseudo SRAM is connected,
specifies the minimum number of cycles after CE is negated before next assert. When
synchronous DRAM is connected, specifies the minimum number of cycles after precharge
until bank active command is output. See section 7.5, Synchronous DRAM Interface, for
details.
Bit 15 (TRP)
0
1
• Bit 14—RAS-CAS Delay (RCD): When DRAM is connected, specifies the number of cycles
after RAS is asserted before CAS is asserted. When pseudo SRAM is connected, specifies the
number of cycles after CE is asserted before BS is asserted. When synchronous DRAM is
connected, specifies the number of cycles after a bank active (ACTV) command is issued
until a read or write command (READ, READA, WRIT, WRITA) is issued.
Bit 14 (RCD)
0
1
130 Hitachi
15 14
TRP RCD TRWL
0 0
R/W R/W
7 6
AMX2 SZ AMX1
0 0
R/W R/W
Description
1 cycle (Initial value)
2 cycles
Description
1 cycle (Initial value)
2 cycles
13 12
TRAS1 TRAS0
0 0
R/W R/W R/W
5 4
AMX0 RFSH
0 0
R/W R/W R/W
11 10
BE RASD
0 0
R/W R/W
3 2
RMD
0 0
R/W
9 8
—
0 0
R
1 0
— —
0 0
R R