Hitachi SH7095 Hardware User Manual page 416

Table 15.9 Bus Timing With PLL Off (CKIO output)
(Conditions: V
Item
Wait setup time
Wait hold time
RAS delay time 1 (SDRAM)
RAS delay time 3 (DRAM)
CAS delay time 1 (SDRAM)
CAS delay time 3 (DRAM)
DQM delay time
CKE delay time
CE delay time 2
OE delay time 2
IVECF delay time
Address input setup time
Address input hold time
*
BS input setup time
*
BS input hold time
Read write input setup time
Read write input hold time
Data buffer on time
Data buffer off time
Address hold time 1
Note: When a master and slave are connected with the PLL off, the external address monitor will
not function properly at 28.7 MHz.
= 5.0 V ±10%, Ta = –20 to +75°C) (cont)
CC
Symbol Min
t 22
WTS
t 5
WTH
t —
RASD1
t 3
RASD3
t —
CASD1
t 3
CASD3
t —
DQMD
t —
CKED
t 3
CED2
t —
OED2
t —
IVD
*
t 14
ASIN
*
t 3
AHIN
t 15
BSS
t 3
BSH
*
t 15
RWS
*
t 3
RWH
t —
DON
t —
DOF
t 5
AH1
Max Unit Figures
— ns
— ns
18 ns
18 ns
18 ns
18 ns
18 ns
21 ns
18 ns
18 ns
18 ns
— ns
— ns
— ns
— ns
— ns
— ns
18 ns
18 ns
— ns
15.19, 15.43, 15.55,
15.67, 15.70
15.19, 15.43, 15.55,
15.67, 15.70
15.38
15.47
15.38
15.47
15.38
15.37
15.60
15.60
15.69
15.71
15.71
15.71
15.71
15.71
15.71
15.17, 15.39, 15.48,
15.61
15.17, 15.39, 15.48,
15.61
15.15
Hitachi 405