Operation; Operation In The Watchdog Timer Mode - Hitachi SH7095 Hardware User Manual

Reading from the WTCNT, WTCSR, and RSTCSR: WTCNT, WTCSR, and RSTCSR are
read like other registers. Use byte transfer instructions. The read addresses are H'FFFFFE80 for
the WTCSR, H'FFFFFE81 for the WTCNT, and H'FFFFFE83 for the RSTCSR.
12.3

Operation

12.3.1

Operation in the Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/IT and TME bits of the WTCSR to 1. Software
must prevent WTCNT overflow by rewriting the WTCNT value (normally by writing H'00) before
overflow occurs. If the WTCNT fails to be rewritten and overflows occur due to a system crash or
the like, a WDTOVF signal is output (figure 12.4). The WDTOVF signal can be used to reset the
system. The WDTOVF signal is output for 128 φ clock cycles.
If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when WTCNT overflows. Either a power-on reset or a
manual reset can be selected by the RSTS bit. The internal reset signal is output for 512 φ clock
cycles.
When a watchdog reset is generated simultaneously with input at the RES pin, the software
distinguishes the RES reset from the watchdog reset by checking the WOVF bit in the RSTCSR.
The RES reset takes priority. The WOVF bit is cleared to 0.
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