Bus Arbitration - Hitachi SH7095 Hardware User Manual

performed immediately after a read access, 1 wait cycle is inserted even when 0 is specified for
waits between access cycles.
When the SH7095 shifts to a read cycle immediately after a write, the write data becomes high
impedance when the clock rises, but the RD signal, which indicates the read cycle data output
enable, is not asserted until the clock falls. The result is that no waits are inserted into the access
cycle.
When bus arbitration is being performed, an open cycle is inserted for arbitration, so no wait is
inserted between cycles (figure 7.47).
Figure 7.47 Waits between Access Cycles
7.10

Bus Arbitration

The SH7095 has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device after the bus cycle being executed is completed. In
addition, it also has a bus arbitration function for supporting the connection of two processors.
These are connected to each other as master and slave through bus arbitration, which enables a
multiprocessor system to be implemented with a minimum of hardware.
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