Power-On Sequence - Hitachi SH7095 Hardware User Manual

7.5.8

Power-On Sequence

To use synchronous DRAM, first the mode must be set after the power is turned on. To properly
initialize the synchronous DRAM, the synchronous DRAM mode register must be written to after
the registers of the bus state controller have been first set. The synchronous DRAM mode register
are set using a combination of the RAS/CE, CAS/OE and RD/WR signals. They fetch the value of
the address signal at that time. If the value to be set is X, the bus state controller operates by
writing to address X + H'FFFF8000 from the CPU, which allows the value X to be written to the
synchronous DRAM mode register. Data is ignored at this time, but mode is written using word as
the size. Write any data in word size to the following addresses to set for the burst read single
write supported by the SH7095, a CAS latency of 1 to 3, a sequential wrap type, and a burst length
of 8 or 4 (depending on whether the width is 16 bits or 32 bits).
For 16 bits: CAS latency 1
CAS latency 2
CAS latency 3
For 32 bits: CAS latency 1
CAS latency 2
CAS latency 3
Figure 7.26 Self-Refresh Timing
H'FFFF8426
H'FFFF8446
H'FFFF8466
H'FFFF8848
H'FFFF8888
H'FFFF88C8
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