Examples Of Use; Dma Transfer Between On-Chip Sci And External Memory; Notes - Hitachi SH7095 Hardware User Manual

• The DMA master enable (DME) bit in the DMAOR is cleared to 0.
Clearing the DME bit in the DMAOR forcibly aborts the transfers on all channels at the end
of the current bus cycle. When the transfer is the final transfer, TE = 1 and the transfer ends.
9.4

Examples of Use

9.4.1

DMA Transfer Between On-Chip SCI and External Memory

In the following example, data received on the on-chip serial communications interface (SCI) is
transferred to external memory using DMAC channel 1. Table 9.9 shows the transfer conditions
and register settings.
Table 9.9 Register Settings for Transfers between On-Chip SCI and External Memory
Transfer Conditions
Transfer source: RDR of on-chip SCI
Transfer destination: external memory (word space)
Number of transfers: 64
Transfer destination address: incremented
Transfer source address: fixed
Bus mode: cycle-steal
Transfer unit: byte
DEI interrupt request generated at end of transfer (DE = 1)
Channel priority: Fixed (0 > 1) (DME = 1)
Transfer request source (transfer request signal): SCI (RXI)
Note: Check the CPU interrupt level when interrupts are enabled in the SCI.
9.5

Notes

1. DMA request/response selection control registers 0 and 1 (DRCR0 and DRCR1) should be
accessed in bytes. All other registers should be accessed in longword units.
2. Before rewriting CHCR0, CHCR1, DRCR0, and DRCR1, first clear the DE bit of the
specified channel to 0 or clear the DME bit of the DMAOR to 0.
3. When the DMAC is not operating, the NMIF bit of the DMAOR is set even when an NMI
interrupt is input.
4. When the cache is used as the on-chip RAM, the DMAC cannot access this RAM.
5. Set to standby mode after the DME bit of the DMAOR is set to 0.
6. Do not access the DMAC, BSC, and UBC on-chip peripheral modules.
274 Hitachi
Register Setting
SAR1 H'FFFFFE05
DAR1 Destination address
TCR1 H'0040
CHCR1 H'4045
DMAOR H'0001
DRCR1 H'01