Hitachi SH7095 Hardware User Manual page 523

DMAC
DMA operation register (DMAOR)
Item 31
Bit name –
Initial Value 0
R/W R
Item 15
Bit name –
Initial Value 0
R/W R
Note: The only writing permitted is 0 to clear the flag.
Bit Bit Name
3 Priority mode bit (PR)
2 Address error flag bit
(AE)
1 NMI flag bit (NMIF)
0 DMA master enable bit
(DME)
512 Hitachi
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30 29 28 27
– – – –
0 0 0 0
R R R R
14 13 12 11
– – – –
0 0 0 0
R R R R
Value
0
1
0
1
0
1
0
1
Bit
26 25 24 23
– – – –
0 0 0 0
R R R R
10 9 8 7
– – – –
0 0 0 0
R R R R
Fixed priority (Ch 0 > Ch 1) (initial value)
Round-robin mode (Top priority shifts to bottom after
each transfer)(The priority for the first DMA transfer after
a reset is Ch 1 > Ch 0)
No DMAC address error (initial value)
Address error by DMAC
No NMIF interrupt (initial value) To clear the NMIF bit,
read 1 from it and then write 0.
NMIF has occurred
Disables DMA transfers on all channels (initial value)
Enables DMA transfers on all channels
32
22 21 20 19
– – – –
0 0 0 0
R R R R
6 5 4 3
– – – PR AE NMIFDME
0 0 0 0
R R R R/W R/
Description
18 17 16
– – –
0 0 0
R R
2 1 0
0 0 0
R/ R/W
(W)* (W)*