Hitachi SH7095 Hardware User Manual page 104

On-Chip Interrupt Sources: The operation of pipelines also must be taken into account to
ensure that the same interrupt does not occur again when the interrupt source is from an on-
chip peripheral module. At least 2 cycles is required fro the CPU to recognize that the
interrupt is from an on-chip peripheral module. 2 cycles are also required for the fact that
there is no longer an interrupt request to be relayed.
• Returning from interrupt processing with an RTE instruction: Figure 5.13 shows how an
extra 1 cycle is required after the read instruction used for synchronization before
interrupts are accepted, even when an RTE instruction is executed. A read instruction for
synchronization should thus be executed between the source clear and the RTE
instruction.
• Changing the level during interrupt processing: Figure 5.14 shows how a minimum
interval of 2 cycles is required between the synchronization instruction and the LDC
instruction when an LDC instruction is used to enable another overlapping interrupt by
changing the SR value. A read instruction for synchronization and a minimum of 2
instructions should thus be executed between the source clear and the LDC instruction.
Figure 5.13 Pipeline Operation during Return with RTE
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