Hitachi SH7095 Hardware User Manual page 240

• Bit 9—Auto Request Mode Bit (AR): This bit selects whether auto-request (generated within
the DMAC) or module request (an external request or from an on-chip SCI module) is used
for the transfer request. The AR bit is initialized to 0 by resets and in the standby mode.
Values are held during a module standby.
Bit 9: AR
0
1
• Bit 8—Acknowledge/Transfer Mode Bit (AM): In the dual address mode, this bit selects
whether the DACK signal is output during the data read cycle or write cycle. In the single-
address mode, it selects whether to transfer data from memory to device or from device to
memory. The AM bit is initialized to 0 by reset and in the standby mode. Values are held
during a module standby.
Bit 8: AM
0
1
• Bit 7—Acknowledge Level Bit (AL): This bit selects whether the DACK signal is an active-
high signal or an active-low signal. The AL bit is initialized to 0 by reset and in the standby
mode. Values are held during a module standby.
Bit 7: AL
0
1
• Bit 6—DREQ Select Bit (DS): Selects the DREQ input detection method used. The DS bit is
initialized to 0 by reset and in the standby mode. Values are held during a module standby.
Bit 6: DS
0
1
• Bit 5—DREQ Level Bit (DL): Selects active high signal or active low signal for the DREQ
signal. The DL bit is initialized to 0 by reset and in the standby mode. Values are held during
a module standby.
Description
Module request mode (Initial value)
Auto request mode
Description
DACK output in read cycle/transfer from memory to device (Initial value)
DACK output in write cycle/transfer from device to memory
Description
DACK is an active-low signal (Initial value)
DACK is an active-high signal
Description
Detected by level (Initial value)
Detected by edge
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