Hitachi SH7095 Hardware User Manual page 6

7.1.3 Pin Configuration ................................................................................. 120
7.1.4 Register Configuration........................................................................... 121
7.1.5 Address Map ....................................................................................... 122
7.2 Description of Registers.................................................................................... 124
7.2.1 Bus Control Register 1 (BCR1) ............................................................... 124
7.2.2 Bus Control Register 2 (BCR2) ............................................................... 126
7.2.3 Wait Control Register (WCR) ................................................................. 128
7.2.4 Individual Memory Control Register (MCR).............................................. 130
7.2.5 Refresh Timer Control/Status Register (RTCSR) ........................................ 134
7.2.6 Refresh Timer Counter (RTCNT) ............................................................ 135
7.2.7 Refresh Time Constant Register (RTCOR) ................................................ 136
7.3 Access Size and Data Alignment ........................................................................ 136
7.3.1 Connections to Ordinary Devices............................................................. 136
7.3.2 Connections to Little Endian Devices ....................................................... 138
7.4 Accessing Ordinary Space................................................................................. 139
7.4.1 Basic Timing ....................................................................................... 139
7.4.2 Wait State Control ................................................................................ 143
7.5 Synchronous DRAM Interface ........................................................................... 145
7.5.1 Synchronous DRAM Direct Connection.................................................... 145
7.5.2 Address Multiplex ................................................................................ 147
7.5.3 Burst Read .......................................................................................... 148
7.5.4 Single Read ......................................................................................... 151
7.5.5 Write.................................................................................................. 152
7.5.6 Bank Active......................................................................................... 154
7.5.7 Refreshes ............................................................................................ 160
7.5.8 Power-On Sequence .............................................................................. 163
7.5.9 Phase Shift by PLL ............................................................................... 165
7.6 DRAM Interface.............................................................................................. 168
7.6.1 DRAM Direct Connection...................................................................... 168
7.6.2 Address Multiplex ................................................................................ 170
7.6.3 Basic Timing ....................................................................................... 171
7.6.4 Wait State Control ................................................................................ 172
7.6.5 Burst Access........................................................................................ 174
7.6.6 Refresh Timing .................................................................................... 176
7.6.7 Power-On Sequence .............................................................................. 177
7.7 Pseudo-SRAM Interface ................................................................................... 178
7.7.1 Pseudo-SRAM Direct Connection............................................................ 178
7.7.2 Basic Timing ....................................................................................... 181
7.7.3 Wait State Control ................................................................................ 182
7.7.4 Burst Access........................................................................................ 184
7.7.5 Refresh............................................................................................... 185
7.7.6 Power-On Sequence .............................................................................. 187
7.8 Burst ROM Interface ........................................................................................ 187
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