Hitachi SH7095 Hardware User Manual page 175

Figure 7.27 shows the mode register setting timing.
Writing to address X + H'FFFF8000 first issues an all-bank precharge command (PALL) for Tp
cycles, then issues a mode register write command for Tmw cycles. When the TRP of the MCR is
set to 1, a single idle cycle is inserted between the Tp cycle and the Tmw cycle.
Before setting the mode register, an idle time of 100 µs (differs by memory manufacturer) must be
assured after the power required by the synchronous DRAM is turned on. When the pulse width of
the reset signal is longer than the idle time, the mode register may be set immediately without
problem. The dummy auto-refresh cycle must run at least as long as the number set by the
manufacturer (usually 8). After setting the auto refresh, it is usual for this to occur naturally during
the various initializations, but there is a way to set the interval when the refresh request is made to
less than the period the dummy cycle is running. Because the address counter within the
synchronous DRAM is not initialized when the auto refresh is used during single read or write
accesses, it must always be an auto-refresh cycle.
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