Hitachi SH7095 Hardware User Manual page 277

Transfer Width: Byte, word, longword
Transfer bus mode: Cycle steal mode
Transfer address mode: Dual mode
DREQ detection method: Level detection
DACK output timing: DMAC write cycle
Bus cycle: Basic bus cycle
Note: Request detection
Figure 9.42 Timing of DREQ Pin Input Detection in Cycle Steal Mode
with Level Detection (2)
The next request can be detected 2 cycles after DACK output (figure 9.42).
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