Hitachi SH7095 Hardware User Manual page 257

Note: When DACK is output in the read cycle, external memory space → external memory
space
Figure 9.9 DMA Transfer Timing in the Dual Address Mode
Bus Modes:
There are two bus modes: cycle-steal and burst. Select the mode with the TB bits of CHCR0 and
CHCR1.
• Cycle-Steal Mode
In the cycle-steal mode, the bus right is given to another bus master after the DMAC transfers
one transfer unit (byte, word, longword, 16-bytes). When another transfer request occurs, the
bus rights are retrieved from the other bus master and another transfer is performed for one
transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is
repeated until the transfer end conditions are satisfied.
The cycle-steal mode can be used with all categories of transfer destination, transfer source,
and transfer request source. The CPU may take the bus twice when an acknowledge signal is
output during the write cycle or in the single address mode. Figure 9.10 shows an example of
DMA transfer timing in the cycle-steal mode (dual address mode, DREQ level detection).
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