Vector Number Setting Register Wdt (Vcrwdt); Vector Number Setting Register A (Vcra) - Hitachi SH7095 Hardware User Manual

5.3.3

Vector Number Setting Register WDT (VCRWDT)

The vector number setting register WDT (VCRWDT) is a 16-bit read/write register that sets the
WDT interval interrupt and BSC compare match interrupt vector numbers (0–127). VCRWDT is
initialized to H'0000 on reset. It is not initialized in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
• Bits 15, 7—Reserved bits: These bits always read 0. The write value should always be 0.
• Bits 14 to 8—Watchdog timer (WDT) interval interrupt vector number (WITV6–WITV0):
These bits set the vector number for the interval interrupt (ITI) of the watchdog timer (WDT).
There are seven bits, so the value can be set between 0 and 127.
• Bits 6 to 0—Bus state controller (BSC) compare match interrupt vector number (BCMV6–
BCMV0): These bits set the vector number for the compare match interrupt (CMI) of the bus
state controller (BSC). There are seven bits, so the value can be set between 0 and 127.
5.3.4

Vector Number Setting Register A (VCRA)

The vector number setting register A (VCRA) is a 16-bit read/write register that sets the SCI
receive-error interrupt and receive-data-full interrupt vector numbers (0–127). VCRA is initialized
to H'0000 on reset. It is not initialized in standby mode.
15 14 13
— WITV6 WITV5
0 0
R R/W R/W
7 6
— BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0
0 0
R R/W R/W
12 11
WITV4 WITV3
0 0 0
R/W R/W
5 4 3
0 0 0
R/W R/W
10 9
WITV2 WITV1 WITV0
0 0
R/W R/W
2 1
0 0
R/W R/W
Hitachi 79
8
0
R/W
0
0
R/W