Basic Timing - Hitachi SH7095 Hardware User Manual

7.7.2

Basic Timing

Figure 7.38 shows the basic pseudo SRAM access timing. Tp is the precharge cycle, Tr is the CE
assert cycle, Tc1 is the write data output, BS is the assert cycle and Tc2 is the read data fetch
cycle. When accesses are consecutive, the precharge cycle Tp of the next access overlaps the Tc2
cycle of the previous access, so accesses can be performed in a minimum of 3 cycles each.
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